This invention relates to the use of a stack of IC chips in lieu of a single IC chip in an electronic host system. A major opportunity for this technology is in the field of memory chips, but it can be adapted to other IC chips, such as those used in DSP (digital signal processing) systems and in communication systems. A field of interest is logic devices, such as field programmable gate arrays (FPGA).
Referring to the memory field, the progression of memory chip technology from one generation to the next, e.g., from 4 Megabit (MEG) Dynamic Random Access Memory (DRAM) to 16 Megabit (MEG) DRAM, drives the design of successive generations of computer systems and processors. These generational jumps in memory technology grow progressively more and more expensive (now on the order of $1 billion per generation) for manufacturers of memory chips, because of the relatively fixed planar geometry of single memory chips and the resultant need for more and more geometrically precise semiconductor processing techniques to add features within this confined space.
The present invention is useful with all types of memory chips, including DRAM, SRAM (Static Random Access Memory), EEPROM (Electrically Erased Programmable Read Only Memory), and FLASH, a fast EEPROM. A high priority is the progression of DRAM memories, which are currently being redesigned to go from monolithic 16 MEG units to 64 MEG units. In the current redesign of SRAM memory units, the effort is to go from 1 MEG to 4 MEG units.
The field of logic devices, e.g., FPGAs, is presently limited by the need for greater density of available gates and transistors, in order to perform more complex tasks.